1. Field of the Invention
The present invention relates generally to electrically erasable and programmable non-volatile semiconductor memory devices, and more particularly to an electrically erasable and programmable read only memory having an array of memory cells each of which essentially consists of one transistor.
2. Description of the Related Art
Recently, NAND-cell type EEPROMs have been developed as one of highly integrated electrically erasable and programmable read-only memory (EEPROM) devices. With such EEPROMs, an array of rows and columns of memory cells are divided into a plurality of cell sections coupled to parallel bit lines. Each cell section includes a predetermined number of memory cell transistors that are connected in series to one another with each of intermediate active layers acting as the source and drain of adjacent memory cell transistors. Each memory cell transistor may be a floating-gate metal oxide semiconductor field effect transistor having an insulated gate (floating gate) for storing electrical charge carriers therein and a control gate coupled to a corresponding word line.
The NAND cell array is arranged either in a P type silicon substrate or in a P type well region formed in an N type silicon substrate. A memory cell transistor positioned at the first end of each NAND cell section has a drain coupled to a corresponding bit line by way of a first select transistor. The source of another memory cell transistor that is at the opposite end of the NAND cell section is coupled to a common source voltage (a reference potential wiring line) through a second select transistor. The control gate electrodes of NAND memory cell transistors are connected to each other along the row direction to constitute word lines on the substrate.
The operation of the conventional NAND-cell type EEPROM arranged as described above is as follows. A data write for a selected cell section is carried out in such a manner that the memory cell transistors included therein are sequentially subjected to write operations with a memory cell transistor that is most distant from the memory cell transistor connected through the first select transistor to a corresponding bit line associated therewith (i.e., the memory cell transistor coupled to the common source potential through the second select transistor) serving as a starting cell transistor. A boosted high voltage Vpp (20 volts, for example) is applied to the control gate of a memory cell transistor being presently selected for writing. An intermediate voltage VppM (such as 10 volts) is applied to the select gate and the control gate(s) of one or more of the memory cell transistors which are positioned between the selected cell transistor and the first select transistor, thereby to render these transistors conductive. A zero-volt voltage or the intermediate voltage VppM is applied to the corresponding bit line in accordance with the logic value of the write data.
When the zero-volt voltage is applied to the bit line, a resultant potential thereon is transferred to the drain of the presently selected memory cell transistor through the transistors being rendered conductive. Electrons are thus injected from the drain into the floating gate of the selected cell transistor. The threshold voltage of it is thus shifted positively. This positive shift condition is defined as a logic "1" storage state. Alternatively, when the intermediate voltage VppM is applied to the bit line, the injection of electrons does not take place, so that the selected cell transistor is kept unchanged in its threshold voltage. This condition is defined as a logic "0" storage state.
A data erase is carried out so that all the memory cell transistors included in the NAND-cell type EEPROM are erased at a time. More specifically, while the control gates and the first and second select gates are set at zero volts, (1) the bit lines and the common source line are rendered electrically floating, and (2) the high voltage vpp is applied to the P type substrate (or both the P type well region and the N type substrate). As a result, electrons accumulated in the floating gates are released to the P type substrate (or to the P type well region) in all the memory cell transistors, causing their threshold voltages to be shifted negatively.
A data read is performed by detecting whether or not a current flows in a selected memory cell transistor while causing the control gate of the selected cell transistor to be at zero volts, and applying a power supply voltage Vcc (5 volts, for example) to the control gates of the remaining memory cell transistors and the select gates.
As is apparent from the above explanation, according to the presently available NAND-cell type EEPROM, the non-selected memory cell transistors act as "transfer gates" that allow the write data to be transferred to or from the selected memory cell transistor during the write and read periods. From this viewpoint, the following inevitable restriction is put on the setting of an allowable range of the threshold voltage of the once-written memory cell transistor: The threshold voltage of a memory cell transistor being written with a logic "1" should range from 0.5 to 3.5 volts. By taking into account the deterioration with age in the threshold voltage after the completion of data write, possible deviations in the manufacturing parameters of the memory cell transistors, a potential variation of the power supply voltage Vcc, and so on, it is required in reduction to practice that the allowable variation range of the threshold voltage is so designed as to be narrower than the above.
However, with a conventional write scheme using a fixed writing potential and a fixed writing time with respect to all the memory cell transistors to cause them to be written under the same conditions, it is not easy to force the threshold voltage variation after writing of a logic "1" to fall within the limited allowable range. For example, the memory cell transistors may vary in physical property due to some variations that possibly occur in the manufacturing processes. Regarding the write characteristic, this causes easy-to-write cells and difficult-to-write cells to coexist in the NAND cell section. To facilitate a successful programming for such cells different in write characteristic from one another, a specific "variable write-time/verify" programming architecture has been proposed which includes a process of adjusting the writing time with respect to each memory cell according to its inherent write characteristic, and a process of checking or verifying the validity of the data once written into each each cell. Unfortunately, the conventional NAND-cell EEPROM still cannot take the maximum advantages out of the advanced programming architecture while maintaining the highest possible integration density. The main reason for this is that EEPROM is conventionally required to include two extra flip-flop circuits that are arranged at the both ends of each bit line to perform a data latch operation and a sense amplification operation. The number of such extra circuits will increase as the number of bits increases. The addition of the increased number of extra circuits leads to an undesirable increase in the occupation area of the internal circuitry of the EEPROM, causing its integration density to decrease.